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LSI/CSI
UL
(R)
LS7362
(631) 271-0400 FAX (631) 271-0405
September 1999
LSI Computer Systems, Inc. 1235 Walt Whitman Road, Melville, NY 11747
A3800
BRUSHLESS DC MOTOR COMMUTATOR/CONTROLLER
FEATURES: * Speed Control by Pulse Width Modulation (PWM) of low-side drivers only. * Open or closed loop motor speed control. * +5 to +28 Volt operation (Vss - VDD). * Externally selectable input to output code for 60, 120, 240, or 300 electrical sensor spacing. * Three or four phase operation. * Analog Speed control. * Forward/Reverse control. * Output Enable control. * Positive Static Braking. * Overcurrent Sensing. * Six outputs drive switching bridge directly. * LS7362 (DIP); LS7362-S (SOIC); LS7362-TS (TSSOP) - See Connection Diagram
CONNECTION DIAGRAM - TOP VIEW STANDARD 20 PIN PLASTIC DIP
CS1 OUT 1 OUT 2 OUT 3 COMMON OUT 4
1 2 3
20 19 18
CS2 FORWARD/REVERSE V DD (-V)
LSI
4
17
S3 S2 S1 OSCILLATOR
LS7362
5 6
16 15 14
OUT 5 OUT 6 BRAKE
7
8 9
13 12 11
V TRIP OVERCURRENT SENSE V SS (+V)
DESCRIPTION:
The LS7362 is a monolithic, ion implanted MOS circuit designed to generate the signals necessary to control a three phase or four phase brushless DC motor. It is the basic building block of a brushless DC motor controller. The circuit responds to changes at the SENSE inputs, originating at the motor position sensors, to provide electronic commutation of the motor windings. Pulse width modulation (PWM) of low-side drivers for motor speed control is accomplished through either the ENABLE input or through the V TRIP input (Analog Speed control) in conjunction with the OSCILLATOR input. Overcurrent circuitry is provided to protect the windings, associated drivers and power supply. The LS7362 circuitry causes the external output drivers to switch off immediately upon sensing the overcurrent condition, and on again only when the overcurrent condition disappears and the positive edge of either the ENABLE input or the sawtooth OSCILLATOR occurs. This limits the overcurrent sense cycling to the chopping rate of the ENABLE input or the sawtooth OSCILLATOR. A positive braking feature is provided to effect rapid deceleration. The LS7362 is designed for driving Bipolar and Field Effect Transistors. Because only low-side drivers are pulse width modulated, the LS7362 is ideally suited in situations where the integrated circuit interfaces with level converters to drive high voltage brushless DC motors. By pulse width modulating the low-side drivers only, the switch losses in the level conversion circuitry for the high-side drivers is minimized. Figure 1 indicates how the level conversion is accomplished.
7362-041100-1
ENABLE 10
The COMMON, Pin 5, is tied to the positive supply rail and LS7362 Outputs 1, 2, and 3 are used to drive level converters Q101, Q102 and Q103 respectively. Only the motor top side drivers consisting of Q107, Q108 and Q109 which are connected to the motor power supply, VM, will be subject to the high speed switching currents that flow through the motor. The level converters are turned on and off at the slower commutation rate. INPUT/OUTPUT DESCRIPTION: COMMUTATION SELECTS (Pins 1, 20) These inputs are used to select the proper sequence of outputs based on the electrical separation of the motor position sensors. With both inputs low (logic zero), the sequence is adjusted for 60 electrical separation, with CS2 high and CS1 low 120 separation sequence is selected, with CS1 high and CS2 low 240 separation sequence is selected and with CS1 and CS2 high the 300 separation sequence is selected. Note that in all cases the external output drivers are disabled for invalid SENSE input codes. Internal pull down resistors are provided at Pins 1 and 20 causing a logic zero when these pins are left open.
FORWARD/REVERSE (Pin 19) This pin acts to modify the input to output sequence such that when brought from high to low or low to high the direction of rotation will reverse. An internal pull up resistor is provided at Pin 19 causing a logic one when left open. SENSE INPUTS (Pins 15, 16, 17) These inputs provide control of the output commutation sequence as shown in Table III. S1, S2, S3 originate in the position sensors of the motor and must sequence in cycle code order. Hall switch "pull-up" resistors are provided at Pins 15, 16 and 17. The positive supply of the Hall devices should be common to the chip Vss. BRAKE (Pin 9) A high level applied to this input unconditionally turns off outputs 1, 2 and 3 and turns on outputs 4,5 and 6 (See Figure 1). Transistors Q101, Q102 and Q103 cut off causing Q107, Q108 and Q109 to cut off and transistors Q104, Q105 and Q106 turn on, shorting the windings together, The BRAKE has priority over all other inputs. An internal pull down resistor is provided at Pin 9 causing no braking when left open. (Center- tapped motor configuration requires a power supply disconnect transistor controlled by the BRAKE signal - See Figure 3.) ENABLE (Pin 10) A high level on this input permits the output to sequence as in Table III, while a low disables all external output drivers. An internal "pull up" resistor is provided at Pin 10, enabling when left open. Positive edges at this input will reset the overcurrent flip-flop. OVERCURRENT SENSE (Pin 12) This input provides the user a way of protecting the motor winding, drivers and power supply from an overload condition. The user provides a fractional ohm resistor between the negative supply and the common emitters of the NPN drivers. This point is connected to one end of a potentiometer (e.g. 100K ohms), the other end of which is connected to the positive supply. The wiper pickoff is adjusted so that all outputs are disabled for currents greater than the limit. The action of the input is to disable all external output drivers. When BRAKE exists, OVERCURRENT SENSE will be overridden. The overcurrent circuitry latches the overcurrent condition. The latch may be reset by the positive edge of either the sawtooth OSCILLATOR or the ENABLE input. When using the ENABLE input as a chopped input, the OSCILLATOR pin should be held at VSS. When the ENABLE input is held high, the OSCILLATOR must be used to reset the overcurrent latch. V TRIP (Pin 13) This pin is used in conjunction with the sawtooth oscillator provided on the circuit. When the voltage level applied to V TRIP is more negative than the waveform at the OSCILLATOR pin, the low-side drivers will be enabled. When V TRIP is more positive than the sawtooth OSCILLATOR waveform the low-side drivers are disabled.
The sawtooth waveform at the OSCILLATOR pin typically varies from .4 Vss to Vss-2 Volts (assuming VDD is at ground potential). The purpose of the V TRIP input in conjunction with the OSCILLATOR is to provide variable speed adjustment for the motor by means of PWM of the low-side drivers. OSCILLATOR (Pin 14) A reisistor and capacitor connected to this pin (See Fig. 6) provide the timing components for a sawtooth OSCILLATOR. The signal generated is used in conjunction with V TRIP to provide PWM for variable speed applications and to reset the overcurrent condition. OUTPUTS 1, 2, 3 (Pins 2, 3, 4) These open drain outputs are enabled as shown in Table III and provide base current when the COMMON (Pin 5) is tied to Vss. These outputs provide commutation only for the high-side drivers. They are not pulse width modulated to control speed. OUTPUT 4, 5, 6 (PINS 6, 7, 8) These open drain outputs are enabled as in Table III and provide base current to NPN transistors when the COMMON is tied to Vss. They provide commutation and are pulse width modulated to provide speed control. COMMON (Pin 5) The COMMON is connected to Vss for driving low-side drivers and high-side level converters. Vss (Pin 11) Supply voltage positive terminal. VDD (Pin 18) Supply voltage negative terminal.
TYPICAL CIRCUIT OPERATION:
Figure 1 indicates an application using bipolar power transistors. The oscillator is used for motor speed control as explained under VTRIP. Only low-side drive transistors are pulse width modulated during speed control. The outputs turn on in pairs (See Table III). For example, two separate paths are turned on when Q8 and Q4 are on. One path is from the positive supply through Q8, R1 and the base emitter junction of Q101. The second is from the positive supply through Q4, R14, the base emitter junction of Q105 and the fractional ohm resistor to ground. The current in the first path is determined by the power supply voltage, the impedance of Q8, the value of R1 and the voltage drop across the base-emitter junction of Q101 (0.7 Volts for a single transistor or 1.4 Volts for a Darlington Transistor). The current in the second path is determined by the power supply voltage, the impedance of Q4, the value of R14 and the voltage drop across the base-emitter junction of Q105. Table I provides the recommended value for R1; R2, R3, R13, R14, and R15 are the same value. Figure 2 indicates an application where Power FETS are used. The nominal power supply for the LS7362 in this configuration is 15 Volts so that the low side N channel Power FET drivers will have 15 Volts of gate drive. Resistors R13, R14 and R15 serve to discharge the gate capacitance during FET turn-off. The high-side P-channel FET drivers use 15 Volt Zener diodes Z1, Z2 and Z3 to limit the gate drive. Resistors R8, R10 and R12 are the gate capacitance discharge resistors. Table II indicates the minimum value of R13 (=R14=R15) needed as a function of output drive voltage for the low-side drivers.
7362-110292-2
MAXIMUM RATINGS: PARAMETER Storage Temperature Operating Temperature 1. Plastic 2. Ceramic Voltage (any pin to Vss)
SYMBOL TSTG TA TA VMAX
VALUE -65 to +150 -25 to +70 -55 to +125 -30 to +.5
UNIT C C C Volts
DC ELECTRICAL CHARACTERISTICS: (All Voltages Referenced to VDD) Supply Voltage Supply Current (Excluding Outputs) Input Specifications: BRAKE, ENABLE, CS1, CS2 S1, S2, S3, FORWARD/REVERSE Voltage (Logic "1") (Logic "0") OVERCURRENT SENSE (See Note) Voltage (Logic "1") (Logic "0") Oscillator: Frequency Range External Resistor Range SYMBOL VSS IDD RIN VIH VIL VIH VIL Fosc Rosc MIN 5 VSS-1.5 0 (VSS/2)+.25 0 0 22 TYP 4.5 150 1/RC MAX 28 6 VSS VSS-4.0 VSS (VSS/2)-.25 100 1000 UNIT Volts mA K Volts Volts Volts Volts kHz k
NOTE: Theoretical switching point of the OVERCURRENT SENSE input is one half of the power supply determined by an internal bias network in manufacturing. Tolerances cause the switching point to vary plus or minus .25 Volts. After manufacture, the switching point remains fixed within 10 mV over time and temperature. The input switching sensivity is a maximum of 50mV. There is no hysteresis on the OVERCURRENT SENSE input.
TABLE I OUTPUT CURRENT LIMITING RESISTOR SELECTION TABLE POWER OUTPUT CURRENT SUPPLY (VOLTS) 20 15 10 7.5 5 2.5 mA 6 ** ** ** ** ** 2.0 9 ** ** ** .94 1.6 3.2 12 .35 .53 .88 1.2 2.1 4.0 15 .54 .76 1.2 1.7 2.6 5.3 Resistance 18 * 1.0 1.6 2.1 3.2 6.5 (k) 21 * * 1.9 2.5 3.8 7.7 24 * * 2.2 2.9 4.4 9.0 28 * * * 3.5 5.3 10.3
*causes excessive power dissipation **exceeds max current possible for this voltage
TABLE II For Power Supply 5-28 Volts R13 (K ohms) 10 5.1 2.7 Output Voltage Vss -0.5 Vss -1.0 Vss -2.0
CS1 CS2 0 0 ELECTRICAL SEPARATION (-60-) SENSE INPUTS S1 S2 S3 000 100 110 111 011 001 010 101
SEQUENCE SELECT
TABLE III OUTPUT COMMUTATION SEQUENCE THREE PHASE OPERATION CS1 CS2 CS1 CS2 CS1 CS2 FORWARD/REVERSE=1 0 1 1 0 1 1 (-120-) (-240-) (-300-) OUTPUTS DRIVERS S1 S2 S3 S1 S2 S3 S1 S2 S3 ENABLED A B C 001 010 011 O1, O5 + Off 101 110 111 O3, O5 Off + 100 100 110 O3, O4 Off + 110 101 100 O2, O4 + Off 010 001 000 O2, O6 Off + 011 011 001 O1, O6 + Off 000 111 000 111 010 101 ALL DISABLED ALL DISABLED
FORWARD/REVERSE=0 OUTPUTS ENABLED O2, O4 O2, O6 O1, O6 O1, O5 O3, O5 O3, O4 DRIVERS A B C + Off Off + + Off + Off Off + Off +
ALL DISABLED ALL DISABLED
The OVERCURRENT input (BRAKE low) enables external output drivers in normal sequence when more negative than Vss/2 and disables all external output drivers when more positive than Vss/2. The OVERCURRENT is sensed continuously, and sets a flip flop which is reset by the rising edge of the ENABLE input or the sawtooth OSCILLATOR. (See description under OVERCURRENT SENSE.)
7362-110292-3
VM
Vss
11
5
R8
R10
R12
Q107
R7 2 BRAKE 3
O3 O1
Q108
R11
Q109
R9
R1
O2
Q101 R2 R3 R6 L3 A L1 B L2 C Q102 Q103
M O T O R
4 Q8 Q7 R4 Q6 R5
Output Encoder
Q5
Q4
Q3 8 7
O5 O6
R13 R14 R15
Vss
6
O4
Q104
R17
Q105
R18
Q106
12
TO OVERCURRENT ADJUSTMENT
R16
Fractional Ohm Resistor
FIGURE 1. BIPOLAR THREE PHASE OUTPUT DRIVER CIRCUITRY
VM
Vss
R8 11 5
Z1
R10 Q107
Z2
R12 Q108 R11
Z3
Q109
R7 2 BRAKE 3
O1 R1 O2 R2
R9
Q101 Q102 R3 Q103
M O T CO R
4 R4 Q6
O3
R5
R6 L3 A L1 B L2
Output Encoder
Q8
Q7
Q5
Q4
Q3 8 7
O5 O6
Vss
6
O4
Q104 R13
TO OVERCURRENT ADJUSTMENT
Q105 R15 Fractional Ohm Resistor
Q106
12
R14
FIGURE 2. POWER FET THREE PHASE OUTPUT DRIVER CIRCUITRY
7362-101992-4
6
O4 BRAKE BRAKE INPUT O5
9 7
FIGURE 3. SINGLE-ENDED DRIVER CIRCUIT
This configuration requires only one base current limiting resistor connected from the COMMON pin to Vss.
LS7362 5
COMMON O6
Vss
MOTOR SUPPLY
8
FIGURE 4. PRECISION CONTROL BRUSHLESS DC MOTOR DRIVE
19 FORWARD
F/R
IN914
10 REVERSE
LS7362
ENABLE
Inputs form SG1731 or UC1637
2.2K
For controlled acceleration and deceleration of motors in the forward or reverse directions, a motor control pulse width modulator circuit such as the SG1731 or UC1637 can be interfaced with the LS7362. The logical OR gate made up of the resistor-diode network permits the LS7362 to be enabled when either the forward or reverse input is high. By applying the forward input directly to Pin 19, the motor can only operate in the forward direction when the forward input is high and only in the reverse direction when the reverse input is high. Motor direction is determined by relative pulse widths of the forward and reverse inputs while acceleration or deceleration is determined by variations of these widths.
Vss
FROM MOTOR POSITION SENSOR Vss
R1 15 S1
FIGURE 5 CLOSED-LOOP SPEED CONTROLLER
A closed loop system can be configured by differentiating one of the motor position sense inputs and integrating only the negative pulses to form a DC voltage that is applied to the inverting input of an op-amp. The non-inverting input voltage is adjusted with a potentiometer until the resultant voltage at V TRIP causes the motor to run at desired speed. The R2-C1 differentiator, the R3-D1 negative pulse transmitter and the R4-C2 integrator form a frequency to voltage converter. An increase in motor speed above the desired speed causes V TRIP to increase which lowers the duty cycle modulation of the oscillator and the resultant motor speed. A decrease in speed lowers V TRIP and raises the duty cycle modulation and the resultant motor speed. For proper operation, both R5 and R6 should be greater than R4, and R4 in turn should be greater than both R2 and R3. Also the R4-C2 time constant should be greater than the R2-C1 time constant. C3 may be added across R6 for additional V TRIP smoothing.
The information included herein is believed to be accurate and reliable. However, LSI Computer Systems, Inc. assumes no responsibilities for inaccuracies, nor for any infringements of patent rights of others which may result from its use.
R3 D1
R2 C1 C3 R5 R6 13 V TRIP
LS7362
R4
C2
+
Vss Vss
C4 14 EXT. OSCILLATOR
R8
R7
7362-101992-5
CS1 CS2
1 20
COMMUTATION SEQUENCE SELECT LOGIC
4 COMMON 5 8
+V INPUT DECODER FWD/REV 19 OUTPUT ENCODER 6
2 O1
OUTPUT DRIVERS
3 O2 4 O3 5 O4 6 O5 7 O6
S1 15 S2 16 S3 17 BRAKE 9 +V
R ENABLE 10
POSITIVE EDGE DETECTOR +
R
Q
LOW-SIDE DRIVERS
R OVERCURRENT 12 SENSE 13 V TRIP +V .001F
+
S HIGH-SIDE DRIVERS +V
30KHz
14 SAWTOOTH OSCILLATOR GND
11 VSS 18 VDD
33K
FIGURE 6. LS7362 BLOCK DIAGRAM

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